1、使能TIM時鐘
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM*,ENABLE);
2、基礎(chǔ)設(shè)置
TIM_TimeBaseStructure.TIM_Period 計數(shù)值
TIM_TimeBaseStructure.TIM_Prescaler 預(yù)分頻,此值+1為分頻的除數(shù)
TIM_TimeBaseStructure.TIM_ClockDivision = 0 時鐘因子 待做進一步說明
TIM_TimeBaseStructure.TIM_RepetitionCounter = 0 待做進一步說明
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up 向上計數(shù)
TIM_CounterMode_Dowm 向下計數(shù)
TIM_CounterMode_CenterAligned1 中心對齊方式1
TIM_CounterMode_CenterAligned2 中心對齊方式2
TIM_CounterMode_CenterAligned3 中心對齊方式3
TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
3、通道設(shè)置
----------------------------------------------------------------------------------------------
輸出比較 & PWM通道
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing 輸出比較時間模式 (輸出引腳凍結(jié)無效)
TIM_OCMode_Active 輸出比較主動模式 (匹配時設(shè)置輸出引腳為有效電平，當(dāng)計數(shù)值為比較/捕獲寄存器值相同時，強制輸出為高電平)
TIM_OCMode_Inactive; 輸出比較非主動模式 (匹配時設(shè)置輸出引腳為無效電平，當(dāng)計數(shù)值為比較/捕獲寄存器值相同時，強制輸出為低電平)
TIM_OCMode_Toggle 輸出比較觸發(fā)模式 (翻轉(zhuǎn)。當(dāng)計數(shù)值與比較/捕獲寄存器值相同時，翻轉(zhuǎn)輸出引腳的電平)
TIM_OCMode_PWM1 向上計數(shù)時，當(dāng)TIMx_CNT < TIMx_CCR*時，輸出電平有效，否則為無效
向下計數(shù)時，當(dāng)TIMx_CNT > TIMx_CCR*時，輸出電平無效，否則為有效
TIM_OCMode_PWM2 與PWM1模式相反
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Disable 禁止OC*輸出
TIM_OutputState_Enable 開啟OC*輸出到對應(yīng)引腳
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable 互補輸出使能。關(guān)閉OC*N輸出
TIM_OutputNState_Enable 互補輸出使能。開啟OC*N輸出到對應(yīng)的引腳
TIM_OCInitStructure.TIM_Pulse 比較/PWM 通道的值
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; 極性為正
TIM_OCPolarity_Low 極必為負
TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High; 極性為正
TIM_OCNPolarity_Low 極必為負
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set 當(dāng)MOE=0時，如果實現(xiàn)了OC*N，則死區(qū)后OC*=1
TIM_OCIdleState_Reset 當(dāng)MOE=0時，如果實現(xiàn)了OC*N，則死區(qū)后OC*=0
TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleNState_Set 當(dāng)MOE=0時，死區(qū)后OC*N=1
TIM_OCIdleNState_Reset 當(dāng)MOE=0時，死區(qū)后OC*N=0
TIM_OC1Init(TIM2, &TIM_OCInitStructure);
TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Disable); 禁止OC1重裝載,即TIM*_CCR*的數(shù)一經(jīng)寫入立即生效，否則要在下一個更新事件到來后才被裝入寄存器
TIM_CtrlPWMOutputs(TIM1,ENABLE); 如果使用PWM模式，則此句一定不能省
----------------------------------------------------------------------------------------------
輸入捕獲通道
TIM_ICInitStructure.TIM_Channel = TIM_Channel_1
TIM_Channel_2
TIM_Channel_3
TIM_Channel_4
TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising 輸入/捕獲上升沿有效
TIM_ICPolarity_Falling 輸入/捕獲下降沿有效
TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI IC*輸入引腳選擇，針對IC1/IC2有不同的定義
TIM_ICSelection_IndirectTI
TIM_ICSelection_TRC
TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1 輸入模式下，捕獲端口上的每一次邊沿都觸發(fā)一次捕獲
TIM_ICPSC_DIV2 輸入模式下，每2次事件觸發(fā)一次捕獲
TIM_ICPSC_DIV4 輸入模式下，每4次事件觸發(fā)一次捕獲
TIM_ICPSC_DIV8 輸入模式下，每8次事件觸發(fā)一次捕獲
TIM_ICInitStructure.TIM_ICFilter = 捕獲采樣頻率，詳見TIM*_CCMR->IC*F說明
----------------------------------------------------------------------------------------------
死區(qū)設(shè)置
TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable
TIM_OSSRState_Disable
TIM_BDTRInitStructure.TIM_OSSRIState = TIM_OSSRIState_Enable
TIM_OSSRIState_Disable
TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_OFF
TIM_LOCKLevel_1
TIM_LOCKLevel_2
TIM_LOCKLevel_3
TIM_BDTRInitStructure.TIM_DeadTime = 這里調(diào)整死區(qū)大小0-0xff
TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable
TIM_Break_Disable
TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_Low
TIM_BreakPolarity_High
TIM_BDTRInitStructure.TIM_AutomaticOutput= TIM_AutomaticOutput_Enable
TIM_AutomaticOutPut_Disable
4、配置中斷
5、開啟TIM
----------------------------------------------------------------------------------------------------
例：
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
TIM_OCInitTypeDef TIM_OCInitStructure;
u16 CCR1_Val = 60000;
u16 CCR2_Val = 40000;
u16 CCR3_Val = 20000;
u16 CCR4_Val = 10000;
/* TIM2 clock enable */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
/* 基礎(chǔ)設(shè)置*/
TIM_TimeBaseStructure.TIM_Period = 65535; //計數(shù)值
TIM_TimeBaseStructure.TIM_Prescaler = 7200-1; //預(yù)分頻,此值+1為分頻的除數(shù)
TIM_TimeBaseStructure.TIM_ClockDivision = 0x0; //
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; //向上計數(shù)
TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
/* 比較通道1*/
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Inactive; //輸出比較非主動模式
TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; //極性為正
TIM_OC1Init(TIM2, &TIM_OCInitStructure);
TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Disable); //禁止OC1重裝載,其實可以省掉這句,因為默認是4路都不重裝的.
/*比較通道2 */
TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
TIM_OC2Init(TIM2, &TIM_OCInitStructure);
TIM_OC2PreloadConfig(TIM2, TIM_OCPreload_Disable);
/* 比較通道3 */
TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
TIM_OC3Init(TIM2, &TIM_OCInitStructure);
TIM_OC3PreloadConfig(TIM2, TIM_OCPreload_Disable);
/* 比較通道4 */
TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
TIM_OC4Init(TIM2, &TIM_OCInitStructure);
TIM_OC4PreloadConfig(TIM2, TIM_OCPreload_Disable);
/*使能預(yù)裝載*/
TIM_ARRPreloadConfig(TIM2, ENABLE);
/*預(yù)先清除所有中斷位*/
TIM_ClearITPendingBit(TIM2, TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4|TIM_IT_Update);
/* 4個通道和溢出都配置中斷*/
TIM_ITConfig(TIM2, TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4|TIM_IT_Update, ENABLE);
/* 允許TIM2開始計數(shù) */
TIM_Cmd(TIM2, ENABLE);
