Signoff 介紹——IR Drop(2)

mzsm 2022-06-22 發(fā)布于湖北

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本公眾號【讀芯樹：duxinshu_PD】主要介紹數(shù)字集成電路物理設(shè)計(jì)相關(guān)知識，才疏學(xué)淺，如有錯誤，歡迎指正交流學(xué)習(xí)。

這是集成電路物理設(shè)計(jì)的第五個系列【signoff】的第十四篇文章，本篇文章主要介紹Static IR Analysis相關(guān)內(nèi)容：

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Static IR Drop Analysis

芯片電路在直流工作模式下的IR Drop分析。
Static IR Drop Analysis: static power calculation + static rail analysis
Static Power Calculation: 計(jì)算某段時間的平均功耗。
Static Rail Analysis: 計(jì)算某段時間平均功耗對應(yīng)的平均電壓降。
Static IR Drop計(jì)算方法：
計(jì)算power/ground network的電阻值。
計(jì)算每個instance的平均電流值(Iavg=Pavg/Vsupply)。
通過歐姆定律計(jì)算每個instance的電壓值(Vstatic=Iavg*R)
Wire/Via EM在static current density之后計(jì)算。

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Static IR Drop Flow

Data Preparation
def：cell placement + power grid
lef: tech section and all macros used in design
lib: for power calculation
ploc: location of ideal power/ground sources
spf: signal nets parasitics (options)
tech: apache technology file
timing: instance slew/frequency + clock (optional for static)
Design Import
>import gsr GENERIC.gsr
>setup design
Power Calculation
>perform pwrcalc
Power Grid Extraction
>perform extraction -power -ground
Package Parasitics (for package wirebond and pads)
>setup package -power -r 0.005 -l 2.5 -c 5
>setup package -ground -r 0.005 -l 2.5 -c 5
>setup wirebond -power -r 0.01 -l 2.2 -c 1.42
>setup wirebond -ground -r 0.015-l 1.7 -c 0.2
>setup pad -power -r 0.001
>setup pad -ground -r 0.001
Static IR/EM Analysis
>perform analysis -static
Result Exploration
result summary
log message viewer
results maps
text results
RedHawk Explorer

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Redhawk cmd

bsub -n 8 -Is readhawk -f static.tcl -P topname##################static.tcl##################import gsr static.gsrsetup designsetup analysis_mode static

perform pwrcalcperform extraction -power -ground

#for package, wirebond, and padssetup package -power -r 0.005 -l 2.5 -c 5setup package -ground -r 0.005 -l 2.5 -c 5setup wirebond -power -r 0.01 -l 2.2 -c 1.42setup wirebond -ground -r 0.015-l 1.7 -c 0.2setup pad -power -r 0.001setup pad -ground -r 0.001

perform analysis -staticexplore designexport db ir_staticexit

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Global System Requirement

APACHE_FILES cleanCACHE_DIR ./tmpMULTI_THREADS 8TEMPERATURE 85TECHNOLOGY 12ENABLE_ATE 0USE_DEF_VIARULE 1USE_LIB_MAX_CAP 1REXTRACTION_DETAIL_LEVEL 1EXTRACT_INTERNAL_NET 1SPLIT_VIA_ARRAY VIA1 0.01MERGE_VIA_METAL 1VIA_BASED_PIN_CURRENT_DIST 1LOWEST_METAL M1ITERATIVE_SOLVER 0
IGNORE_LEF_DEF_MISMATCH 1IGNORE_LIB_CHECK 1IGNORE_DEF_ERROR 1IGNORE_PGARC_ERROR 1IGNORE_GDSMEM_ERROR 0PUSH_PININST 1PUSG_PG_PININST 1ADD_LEF_CELL_FOR_POWER 0DEF_TRUE_PATH_EXTENSION 1
TOP_CELL design_nameFREQ 500e6TOGGLE_RATE 0.3 2.0INPUT_TRANSITION 0.1nsVDD_NETS {VDD 0.8}GND_NETS {VSS 0}
TEMPERATURE_EM 110EM_LENGTH_USE_MAX_LENGTH 1USE_DRAWN_WIDTH_FOR_EM 1USE_DRAWN_WIDTH_FOR_EM_LOOKUP 1
TECH_FILE {apache_design.tech}LEF_FILES {tech.lef cell.lef}LIB_FILES {cell1.lib cell2.lib}DEF_FILES {block.def block design.def top}BLOCK_STA_FILES {FREQ_OF_MISSING_INSTANCE 588e6 design_name design.timing}CELL_RC_FILE {cell_name cell.spef design_name design.spef}NET_LOAD_FILE {net_load.list}PAD_FILES {./design.ploc}GDS_FILES {}GSC_FILES {}APL_FILES {}DECAP_CELLS_FILES {dcap_cell.list}IGNORE_CELLS_FILES {fill_cell.list}IGNORE_LEF_CELL_PIN_FILE {ignore_pin.list}
DYNAMIC_SIMULATIN_TIME 10e9DYNAMIC_TIME_STEP 10e12DYNAMIC_PRESIM_TIME -1
VCD_X_LOGIC_STATE 3VCD_TIME_ALIGNMENT 1POWER_VCD_COVERED_THRESHOLD 0.001

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參考文獻(xiàn)

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